1553 Data Bus Cards Multi-Channel 1553 Interface

Key Features:

·     One to Eight Independent, Dual Redundant MIL-STD-1553 Channels

·     Dual Function (BC/Mon or mRT/Mon) or Full Function (BC/mRT/Mon)

·     One Mbyte of Memory per Channel

·     Fully Compliant to MIL-STD-1553B Notice II

·   Transfer data rate  1Mbps & 4Mbps

·     Commercial or Industrial Extended Temperature Parts, Conduction Cooled and Rear Panel Optional

·     Advanced 32-bit BC, RT and Monitor FPGA Design – Full 32 bit Memory.

·     BC Framing/Subframing/Aperiodic

·     Common Data Packets (CDP) for BC, RT and Monitor – Complete Message Info

·     Advanced, Multi-layer API Provided at No Cost with Source Code

·     Windows, Linux, RTOS, LabVIEW & RT

·     .NET Managed DLLs

·     Industry First: 20ns Signal Generation

·     Bit Construction – 1553 PHY TX

·     Advanced BIT Features

·     Full HW Interrupt Features

·     PCI 32 Bit, 33/66MHz

General

·     32-Bit PCI 33/66MHz

·     One Megabyte RAM per Channel

·     Common Data Packets (CDPs) for all BC, RT and Monitor Functions

·     MIL-STD-1553B Notice II

·     Parts Temp (C) : -55 to +120 Storage, 0 to +70 Commercial, -40 to +85 Extended

·     SCSI 3 Cable Assembly with 1553 3-Plug Stub Cables Provided. DB50 Optional for Trig/Clk/IO.

·     Loop-Back & User BIT

·     IRIG-B RX PAM and TX/RX PPS Time Sync

BC Features

·     Simple One-Shot Lists to Advanced Message Framing and Subframing

·     Message Timing with 100 nSec Accuracy

·     Infinite Linked CDP Data Buffers

·     64-Bit, 20 ns Time Tags, Interrupts, Triggers

·     Low and High Priority Aperiodic Messages

·     Multi Branching Per Message, No-Ops, Delays, Ext Trigger In/Out, Interrupts etc⋯

·     Up to 15 Retries Per Message

·     Legal and Reserved Mode Codes

·     1553A and 1553B Support

·     Full Error Injection/Detection

RT Features

·     Infinite Linked CDP Data Buffers

·     64-Bit, 20 ns Time Tags, Interrupts, Triggers

·     Legal and Reserved Mode Codes

·     1553A and 1553B Support

·     Full Buffering of All Mode Codes

·     Full Error Injection/Detection

Monitor

·     Sequential and RT Mapped Monitoring with Infinite Linked CDP Data Buffers

·     Available with All Card Models

·     64-Bit, 20 ns Time Tags, Interrupts, Triggers

·     Full Error Detection

Software：Data Bus Analyzer

·     Support Windows 7/10(.Net 2.0) and ANSI C Linux, VxWorks, Integrity, LabVIEW & RT Support, etc⋯

Hardware  Interface

·     Support PCI，3U/6U CPCI/PXI Compliant，PCIE，P104Plus，VPX，etc⋯